The present invention relates to a fully inverted type SOI-MOSFET.
Herein, the term of xe2x80x9cSOI-MOSFETxe2x80x9d means a field-effect transistor that employs a silicon layer provided via an insulating layer on a substrate (this layer is referred to as a xe2x80x9ctop silicon layerxe2x80x9d) as an active region. A gate electrode is provided on the top silicon layer via a gate oxide film. A portion that belongs to the top silicon layer and corresponds to a portion located just under the gate electrode becomes a channel region, and portions located adjacently on both sides of this channel region become a source region and a drain region. The xe2x80x9cfully inverted typexe2x80x9d means a type such that the channel region is inverted throughout the entire thickness (the entire region in the direction of thickness) during operation.
As well-known, there is a short-channel effect as a serious problem in accordance with developments in fine structure generally in MOSFET""s (MOS type field-effect transistor) and accordingly in SOI-MOSFET""s. This short-channel effect itself can be overcome by increasing the impurity concentration in the substrate. If such an arrangement is adopted, there is caused another problem that the threshold voltage rises. In contrast to this, in the fully inverted type SOI-MOSFET, the short-channel effect can be overcome without increasing the impurity concentration nor making the threshold voltage rise (Japanese Patent Laid-open Publication No. HEI 11-284201). That is, in the conventional type SOI-MOSFET shown in FIG. 11A, a line of electric force that has originated from a gate electrode 105 via a gate oxide film 104 terminates in a channel carriers Q1 and ionized impurities Q2 inside a top silicon layer 103 and terminates in impurities Q3 inside a silicon substrate 101 through an embedded oxide film 102. However, in the fully inverted type SOI-MOSFET shown in FIG. 11B, an embedded oxide film 102A is increased in film thickness, and a top silicon layer 103A is reduced in film thickness. Therefore, a channel region 118 that belongs to the top silicon layer 103A and corresponds to a portion located just under the gate electrode 105 is inverted through the entire thickness (the entire region in the direction of thickness), and almost all the lines of electric force that have originated from the gate electrode 105 via the gate oxide film 104 terminate in the channel carriers Q1 inside the top silicon layer 103A. Therefore, in the fully inverted type SOI-MOSFET, the controllability of the channel charges by the gate electric field can be improved, and the short-channel effect can be restrained.
Describing in concrete, the SOI-MOSFET generally has the following three types of operation modes depending on the state inside the top silicon layer. The operation modes include (1) a partially depleted type such that an inversion layer, a depletion layer and a neutral region exist inside a top silicon layer similarly to the bulk MOSFET, (2) a fully depleted type such that only an inversion layer and a depletion layer exist and (3) a fully inverted type such that only an inversion layer is formed. For example, in case that the impurity concentration in the channel region is NA=1017 cmxe2x88x923, there is resulting the (1) partially depleted type when the thickness of the top silicon layer is greater than 1 xcexcm, the (2) fully depleted type when the thickness is not smaller than 100 nm and not greater than 1 xcexcm and the (3) fully inverted type when the thickness is not greater than 10 nm. When the impurity concentration in the channel region differs from NA=1017 cmxe2x88x923, the widths of the depletion layer and the inversion layer are varied, and therefore, the thickness of the top silicon layer that enters each operation mode is also varied. The neutral region and the depletion layer are removed by reducing the film thickness of the top silicon layer, by which the controllability of the inversion layer by the gate electric field is improved to restrain the short-channel effect. Even in the case of a MOSFET of the partially depleted type (1) having a channel length that causes the short-channel effect, the short-channel effect is restrained with the provision of the fully depleted type of (2). Furthermore, even in the case of the MOSFET of this fully depleted type having a channel length that causes the short-channel effect, the short-channel effect is restrained with the provision of the fully inverted type of (3). As described above, in the fully inverted type SOI-MOSFET, the short-channel effect is restrained to enable the threshold voltage to be easily controlled.
An effective mutual conductance Gm during the device operation depends on not only a mutual conductance gm when only the channel region is taken into consideration but also a source resistance RS. The effective mutual conductance Gm of the entire device is expressed as:
Gm=gm/(1+RSgm)xe2x80x83xe2x80x83(1) 
by the mutual conductance gm of the channel region and the source resistance RS. The source resistance RS is expressed as:
RSxcx9cxcfx81sL/dxe2x80x83xe2x80x83(2) 
by a width d in a direction perpendicular to the channel direction of the diffusion layer, a length L in a direction that coincides with the channel direction and a sheet resistance xcfx81s. In the above-mentioned fully inverted type SOI-MOSFET, the top silicon layer 103A is reduced in film thickness so that the top silicon layer 103A is inverted throughout the entire thickness. Therefore, a source region 116 and a drain region 117, which belong to the top silicon layer 103A and are located adjacent to a channel region 118, are concurrently reduced in film thickness. Therefore, in the above-mentioned fully inverted type SOI-MOSFET, the sheet resistance xcfx81s is increased to increase the source resistance RS. The increase in the source resistance RS cancels the increase in the mutual conductance gm of the channel region, and this leads to a problem that the effective mutual conductance Gm and accordingly a current drive power is not increased in spite of the intention. According to the results of calculation carried out by the present inventors by three-dimensional device simulation, as shown in FIG. 4, the effective mutual conductance Gm is rather reduced when a film thickness tSi of the top silicon layer is reduced to 10 nm or less, and the current drive power is consequently reduced.
Accordingly, the object of the present invention is to provide a fully inverted type SOI-MOSFET capable of increasing the effective mutual conductance (Gm).
In order to achieve the aforementioned object, the present inventors paid attention to the reduction in resistance of the source region. In the standard semiconductor processes, the source region and the drain region are formed symmetrically on both sides of the channel region. However, from the point of view of mutual conductance based on the equation (1), there is no influence exerted even when the drain resistance is made different from the source resistance. Accordingly, there is required no specific consideration for a limitation on the drain region. It is to be noted that, as a realistic approach, the following analysis is based on the case where the source region and the drain region are formed symmetrically on both sides of the channel region.
First of all, in order to reduce the resistance of the source region itself, the present inventors examined an increase in the impurity concentration of the source/drain region. According to the results of calculation carried out by the present inventors through the three-dimensional device simulation, as shown in FIG. 5, if the impurity concentration ND of the source/drain region is increased from 1020 cmxe2x88x923 to 1021 cmxe2x88x923, then the effective mutual conductance Gm is increased from about 200 mS/mm to 295 mS/mm. The reason for the above is considered to be ascribed to a reduction in the source resistance RS as a consequence of an increase in the impurity concentration of donor impurity of As, P or the like. It was also discovered that the effective mutual conductance Gm reduced as the impurity concentration increased when the impurity concentration ND of the source/drain region exceeded 1021 cmxe2x88x923. The reason for the above is presumably ascribed to the appearance of an electric field component in a direction opposite to a carrier travel direction attributed to a built-in electric field at a boundary (pn junction) formed by the source region and the channel region. FIG. 6 shows an electric field intensity dV/dx (a value multiplied by 103 is expressed in the unit V/cm) in the direction of channel just under the gate oxide film, obtained through calculation. A range in which x=0 to 0.2 xcexcm, a range in which x=0.2 xcexcm to 0.3 xcexcm and a range in which x=0.3 xcexcm to 0.5 xcexcm correspond to the source region, the channel region and the drain region, respectively. As is apparent from FIG. 6, the electric field intensity dV/dx is extremely reduced when x=0.2 xcexcm at the boundary between the source region and the channel region under the condition that the impurity concentration ND of the source/drain region is 1022 cmxe2x88x923. This indicates that an electric field component in the direction opposite to the carrier travel direction has appeared due to the built-in electric field at the pn junction located between the source region and the channel region. This result has substantiated the fact that the effective mutual conductance Gm is increased when the impurity concentration ND of the source/drain region falls within the range of about 1020 cmxe2x88x923 to 1021 cmxe2x88x923 and that the effective mutual conductance Gm is conversely reduced when the impurity concentration ND of the source/drain region exceeds 1021 cmxe2x88x923.
Next, the present inventors examined the construction of the source/drain region of metallic suicide in order to reduce the resistance of the source region itself. FIG. 7 shows the characteristics of a drain current Id/W per unit gate width (a value multiplied by 10xe2x88x923 is expressed in the unit A/gm) with respect to a gate voltage Vg (unit V) when a mobility xcexc is varied in steps as a parameter from about 10 to 10000 xcexcm2/Vsec. As is apparent from FIG. 7, the drain current Id increases as the mobility xcexc increases. In other words, the effective mutual conductance Gm increases as the source resistance RS reduces. Therefore, if the source/drain region is constructed of metallic silicide, then the effective mutual conductance Gm increases.
Moreover, the present inventors examined the reduction in the resistance of the source region by varying the dimensional parameters of the device. As shown in FIGS. 8A and 8B, under the condition that a thickness tFOX of a gate oxide film 14 is fixed to 7 nm, a thickness tBOX of an embedded oxide film 12 is fixed to 1 xcexcm, a gate length LG is fixed to 0.1 xcexcm and a gate width W is fixed to 10 xcexcm, a distance xcex94x in the direction of channel between a metal contact and a gate electrode in the source is varied in three steps of 0.01 xcexcm, 0.05 xcexcm and 0.1 xcexcm, and the thickness tSi of a top silicon layer 13 (including the channel region and the source/drain region) is varied in two steps of 1 nm and 5 nm. FIG. 9 and FIG. 10 show the source/drain region impurity concentration (ND) dependency of the effective mutual conductance Gm (in the unit mS/mm) when the dimensional parameters are varied in steps as described above. As is apparent from FIG. 9, when the distance xcex94x in the direction of channel between the metal contact and the gate electrode is reduced in steps of 0.1 xcexcm, 0.05 xcexcm and 0.01 xcexcm in correspondence with the conditions (D), (C) and (A) shown in FIG. 8A, the effective mutual conductance Gm increases. Moreover, as is apparent from FIG. 10, when the thickness tSi of the top silicon layer 13 is increased from 1 nm to 5 nm in correspondence with the shift of conditions of FIG. 8A from (D) to (E) and (A) to (B), the effective mutual conductance Gm increases. This result substantiated the fact that the mutual conductance Gm was increased by locating the metal contact on the source region close to the gate electrode and increasing the film thickness of the top silicon layer.
From the above result of the analysis, according to the present invention, there is provided a fully inverted type SOI-MOSFET having a channel region constructed of a portion that belongs to a top silicon layer and is located just under a gate electrode and a source region and a drain region, which belong to the top silicon layer and are located adjacent to the channel region, the channel region being inverted throughout the entire thickness thereof during operation, wherein
the source region has a source resistance (RS), which satisfies a relation that (1/gm) greater than RS with respect to a mutual conductance (gm) of the channel region itself.
In the fully inverted type SOI-MOSFET of this invention, the source resistance (RS) satisfies the relation that (1/gm) greater than RS with respect to the mutual conductance (gm) of the channel region itself. Therefore, the effective mutual conductance (Gm) can be improved on the basis of the aforementioned equation (1). As a result, a high-performance device of high current drive power and low consumption of power is obtained.
In one embodiment of the present invention, the source region has an impurity concentration set so that the source resistance (RS) of the source region satisfies the relation that (1/gm) greater than RS with respect to the mutual conductance (gm) of the channel region itself.
In one embodiment of the present invention, the source region contains a metal in the composition thereof so that the source resistance (RS) of the source region satisfies the relation that (1/gm) greater than RS with respect to the mutual conductance (gm) of the channel region itself.
In one embodiment of the present invention, the source region is made of metallic silicide.
In one embodiment of the present invention, the metallic silicide is comprised of at least one of a group consisting of tantalum silicide, niobium silicide, chromium silicide, cobalt silicide, nickel silicide, zirconia silicide, vanadium silicide, hafnium silicide, molybdenum silicide and platinum silicide.
In one embodiment of the present invention, a portion that belongs to the top silicon layer and constitutes the source region has a thickness greater than a thickness of a portion that constitutes the channel region so that the source resistance (RS) of the source region satisfies the relation that (1/gm) greater than RS with respect to the mutual conductance (gm) of the channel region itself.
In one embodiment of the present invention, a distance (xcex94x) in a direction of channel between a metal contact and a gate electrode in the source region is reduced so that the source resistance (RS) of the source region satisfies the relation that (1/gm) greater than RS with respect to the mutual conductance (gm) of the channel region itself.